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VLSI Engineer L3 - Wipro
Hardware Engineer
Senior VLSI Engineer responsible for RTL design, verification, and timing analysis of ASIC and FPGA products using industry‑standard EDA tools. Focus on high‑performance, low‑power silicon solutions.
About the role
Key Responsibilities
- Design, implement, and review RTL modules in Verilog for ASIC and FPGA projects.
- Perform synthesis, place‑and‑route, and timing analysis to meet performance and power targets.
- Collaborate with verification, physical design, and test teams to ensure design integrity.
- Utilize EDA tools (Synopsys, Cadence, Mentor) for simulation, formal verification, and power estimation.
- Document design decisions, create design reviews, and maintain version control.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, VLSI, or related field.
- 3+ years of professional experience in VLSI design and RTL development.
- Strong proficiency in Verilog, timing analysis, and EDA tool workflows.
- Experience with ASIC or FPGA design flows and power optimization.
- Excellent problem‑solving skills and ability to work in a fast‑paced environment.