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VLSI Engineer L3 Contract - Wipro
Hardware Engineer
Experienced VLSI Engineer (Level 3) needed for contract work on high‑performance ASIC projects, focusing on RTL development, synthesis, timing closure, and verification using Verilog/VHDL and industry‑standard EDA tools.
About the role
Key Responsibilities
- Develop and optimize RTL code in Verilog and VHDL for complex ASIC designs.
- Perform synthesis, place‑and‑route, and timing closure using Cadence and Synopsys toolchains.
- Collaborate with cross‑functional teams to define specifications, create testbenches, and execute functional verification.
- Analyze and resolve design issues related to power, performance, and area (PPA) constraints.
- Prepare design documentation, including block diagrams, timing reports, and release notes.
Requirements
- Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or related field.
- 5+ years of hands‑on experience in ASIC/SoC design and verification.
- Proficiency with Verilog/VHDL, synthesis tools (Design Compiler, Genus), and layout tools (Innovus, Encounter).
- Strong understanding of digital signal processing concepts and timing analysis.
- Excellent problem‑solving skills and ability to work independently in a contract environment.