Verification Software Engineer - TrellisWare Technologies

Key Responsibilities

• Develop and maintain verification environments for complex System-on-Chip (SoC) designs.
• Create testbenches, stimulus generators, and verification IP using SystemVerilog and UVM.
• Collaborate with design engineers to define verification strategies and ensure functional correctness.
• Debug and resolve issues found during the verification process.
• Develop and maintain scripts for automation and regression testing.
• Contribute to the improvement of verification methodologies and tools.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Proven experience in ASIC verification using SystemVerilog and UVM.
• Proficiency in scripting languages such as Python.
• Strong understanding of digital design principles and SoC architectures.
• Experience with simulation tools and methodologies.