onsite
Verification Engineer - Siliciom Technologies
Software Engineer
Verification Engineer focused on ASIC design, building robust test benches with System Verilog, UVM, and OVM. Expertise in networking and interface protocols such as PCIe and USB, plus SoC verification, drives rigorous test environments and detailed verification plans.
About the role
Key Responsibilities
- Design, develop, and maintain high‑quality test benches using System Verilog and UVM/OVM frameworks.
- Create comprehensive verification environments and test plans for ASIC and SoC projects.
- Implement and validate networking and interface protocols (PCIe, USB, DDR, MIPI, AXI, SATA) within the verification flow.
- Collaborate with design and firmware teams to troubleshoot and resolve functional issues.
- Document verification results, generate reports, and provide actionable feedback to design teams.
Requirements
- B.E./B.Tech or M.E./M.Tech in ECE/EEE or equivalent.
- Strong experience with System Verilog, UVM, and OVM methodologies.
- Proficiency in scripting languages for automation and test harness development.
- Solid understanding of SoC verification and interface protocol specifications.
- Excellent written and verbal communication skills.