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Verification Engineer - Codasip
Software Engineer
Senior Verification Engineer driving secure, CHERI‑enabled processor development using SystemVerilog, UVM, and ASIC/FPGA testbenches to ensure robust, cyber‑resilient hardware.
About the role
Key Responsibilities
- Design, implement, and maintain comprehensive verification environments for next‑generation secure processors using SystemVerilog and UVM.
- Collaborate with architecture and RTL teams to define test plans, coverage models, and security‑specific verification strategies.
- Execute simulation, emulation, and FPGA prototyping to validate functional and security requirements.
- Analyze debug data, generate reports, and drive root‑cause analysis for design defects.
- Mentor junior verification engineers and contribute to process improvement initiatives.
Requirements
- 5+ years of hardware verification experience in ASIC/FPGA environments.
- Hands‑on experience with simulation/emulation tools (e.g., Questa, VCS, Incisive) and FPGA prototyping.
- Solid understanding of security concepts, including CHERI or similar privilege‑enforced architectures.
- Excellent analytical, communication, and teamwork skills.