Validation / Verification Eng, Sr Staff Engineer - Synopsys

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of Static Timing Analysis, and you know that the difference between a chip that tapes out on schedule and one that doesn't often comes down to a corner case nobody thought to validate three months earlier. You are the engineer who thinks about those corner cases. You have debugged enough PrimeTime runs to know when a timing violation is real and when it's a setup issue, and you can explain the difference to an R&D engineer in two sentences without losing the nuance.

You do not just run regressions. You architect them. You think about what could break under customer conditions that your testbench has never seen, and you build validation strategies that catch those issues before they ship. When an ambiguous bug report comes in from the field, you are the person who can reproduce it, isolate it, and work with R&D to fix it without three rounds of back and forth.

You have learned that AI tools like Cursor and LLMs can accelerate your work, but only if you know what to ask and how to validate what comes back. You use them to write faster, debug smarter, and analyze deeper, but you never ship something you have not personally verified.

At Synopsys, you will own validation for PrimeTime STA features that directly affect whether our customers can sign off their chips. The work is technical, the stakes are real, and the team will rely on your judgment.

What You'll Be Doing

• Own end-to-end validation of complex PrimeTime STA features and flows, from requirement analysis through quality sign-off and customer readiness
• Define validation strategy, coverage depth, and risk-based testing plans for advanced timing scenarios including OCV, AOCV, POCV, path-based analysis, ECO flows, and hierarchical STA
• Lead technical debugging of complex, cross-component issues reported by customers or found in regression, driving root cause analysis and collaborating with R&D to validate fixes
• Architect and enhance automation frameworks using Perl, Tcl, and Python to improve regression robustness, testcase coverage, and validation productivity
• Mentor L1 and L2 validation engineers on STA concepts, debugging techniques, testcase design, and validation best practices