We're looking for an Implementation Engineer focused on designing and building scalable technical solutions. This mid level role requires 8+ years of relevant experience.
About the role
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in ASIC design or RTL design.
Experience with SoC design and integration.
Experience with multi-chiplet SoC integration.
Experience with SoC Design for Testing (DFT) planning.
Experience scripting in Python or Perl or Tcl.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with SoC signoff–Logic Equivalence Check (LEC)/Lint/Unified Power Format (UPF)/CDC/Reset Domain Crossing (RDC) flows.
Cross-functional experience with Design Verification (DV), Physical Design (PD), Clock Domain Crossing (CDC) and DFT teams.
Experience designing and constructing ASIC Input/Output (IO) pad-rings.
Knowledgeable in 3DIO methodology, voltage and clock domain partitioning.
Knowledgeable in ASIC top-level Static Timing Analysis (STA) and clock planning.
Responsibilities
Lead advanced SoC integration projects from concept to final delivery, managing project milestones, deliverables, and cross-functional schedules.
Partner with ASIC teams on complex interposer and package design, and resolve multi-die physical design challenges leveraging 3DIO and domain partitioning expertise.
Utilize software-based construction to seamlessly integrate SoC IPs and maintain complete ownership of the upper-level RTL hierarchy up to the package level.
Collaborate closely with Verification and Emulation teams to resolve complex connectivity issues and optimize system compilation.
Participate in critical layout design decisions and SoC-level sign-off activities to ensure robust, high-performance silicon delivery.