Test Engineer - Efficient Computer

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution

Efficient Computer is a fabless semiconductor startup headquartered in Pittsburgh, PA, building energy-efficient processors for edge compute, embedded AI, and high-performance applications. Our team designs, tapes out, and brings up custom silicon across multiple process nodes, working closely with world-class foundry and OSAT partners to deliver differentiated chips from concept to production. Efficient Computer is looking for a Test Engineer with hands-on DFT and fabless semiconductor test experience to join our Operations team. This is a mid-level role sitting at the intersection of Hardware Engineering and Supply Chain and Operations. The right candidate has worked across the full test lifecycle - from DFT strategy and ATPG pattern generation through ATE bringup, OSAT coordination, and production test - and is equally comfortable working with external suppliers as they are with internal hardware engineers. You will serve as the primary interface between our engineering team and our foundry, OSAT, and test partners, owning test engineering across our active chip programs and scaling that foundation to future products. What You Will Do DFT Strategy and Pattern Development

• Partner with external design partners and internal hardware engineers to define and execute DFT strategy for each chip program
• Generate, validate, and deliver ATPG patterns including scan, MBIST, JTAG, and embedded memory read and write sequences
• Develop and maintain STIL and PDL test program files for ATE execution
• Drive DFT sign-off deliverables and resolve pattern-level issues in coordination with external partners
• Support setup pattern generation including power-up and power-down sequences, DFT entry sequences, and test mode initialization
• Understand and define power rail sequencing requirements for ATE execution to ensure safe device bringup

ATE Bringup and Test Program Development

• Develop and debug test programs on ATE platforms including Advantest and Teradyne systems
• Execute first silicon bringup on new tapeouts in partnership with hardware engineers and OSAT test teams
• Characterize device behavior across voltage, temperature, and frequency corners
• Support load board bring-up and interface hardware validation