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Technical Manager Design Verification - AMD
Engineering Manager
Lead a high‑performance verification team, architecting robust testbenches and environments for next‑generation ASICs and FPGAs using SystemVerilog, UVM, and Python to ensure flawless product delivery.
About the role
Key Responsibilities
- Lead and mentor a multidisciplinary verification team, setting technical direction and ensuring alignment with product roadmaps.
- Design, develop, and maintain scalable UVM‑based testbenches for ASIC and FPGA targets, driving coverage closure and defect detection.
- Collaborate closely with design, synthesis, and physical teams to resolve complex verification issues and optimize performance.
- Implement automated regression frameworks, continuous integration pipelines, and coverage analysis tools to accelerate time‑to‑market.
- Provide technical guidance on emerging verification methodologies, tools, and best practices.
Requirements
- 10+ years of experience in design verification, with a strong background in SystemVerilog and UVM.
- Proven track record managing and scaling verification teams in a fast‑paced semiconductor environment.
- Hands‑on experience with ASIC and FPGA verification, including RTL simulation, formal verification, and emulation.
- Strong scripting skills in Python and familiarity with CI/CD pipelines.
- Excellent communication, leadership, and problem‑solving abilities.