onsite
Technical Lead Manager - Machine Learning & Memory Subsystem Design
ML Engineer
Lead a multidisciplinary team to architect and verify high‑bandwidth memory solutions, integrating machine learning techniques for performance optimization and test coverage enhancement.
About the role
Key Responsibilities
- Architect and oversee the design of DRAM and HBM memory subsystems, ensuring scalability and performance targets are met.
- Lead the development of machine learning models to predict and mitigate memory bottlenecks and reliability issues.
- Drive test design and verification strategies, creating robust testbenches and coverage models for complex memory interfaces.
- Collaborate with cross‑functional teams (ASIC, firmware, software) to integrate memory solutions into larger system architectures.
- Mentor and manage a team of engineers, fostering a culture of innovation and continuous improvement.
Requirements
- 10+ years of experience in memory subsystem design, with deep expertise in DRAM/HBM technologies.
- Proven track record of leading technical teams and delivering high‑quality, high‑performance memory solutions.
- Strong background in machine learning applied to hardware design and verification.
- Excellent communication skills and ability to translate complex technical concepts to stakeholders.