onsite
Technical Architect - Memory Layout Design - HCLTech
Solutions Architect
Technical Architect leading complex memory layout and characterization projects, using Cadence, Synopsys and Mentor Graphics tools to optimize performance, ensure compliance, and guide cross‑functional teams.
About the role
Key Responsibilities
- Lead end‑to‑end memory characterization initiatives, defining methodology, metrics, and validation plans.
- Utilize Cadence, Synopsys, and Mentor Graphics tools to model, simulate, and verify memory architectures.
- Collaborate with design, verification and firmware teams to integrate memory solutions into silicon blocks, ensuring timing and power targets.
- Drive performance optimization and compliance with industry standards (JEDEC, DDR, LPDDR) through detailed analysis and root‑cause debugging.
- Provide technical mentorship, conduct design reviews, and produce documentation for stakeholders and project managers.
Requirements
- 10+ years of experience in memory architecture, layout design, and characterization for ASIC/SoC projects.
- Deep expertise with Cadence, Synopsys, and Mentor Graphics toolchains for memory analysis.
- Strong background in RTL design, timing closure, and low‑power techniques.
- Proven ability to lead cross‑functional teams and communicate complex technical concepts to both engineering and business audiences.
- Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or related field.