Staff Verification Engineer - Media IP - Arm

Key Responsibilities

• Design, develop, and maintain RTL and UVM testbenches for Media IP blocks such as ISPs, display processors, and video codecs.
• Collaborate with IP architects to define verification strategies, coverage models, and functional specifications.
• Execute simulation runs, analyze results, and debug complex RTL issues using industry‑standard tools.
• Generate and maintain detailed verification reports, coverage metrics, and defect logs.
• Mentor junior verification engineers and contribute to process improvements.

Requirements

• 5+ years of experience in ASIC/SoC verification with strong RTL and SystemVerilog skills.
• Proficiency in UVM methodology and testbench development.
• Hands‑on experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium).
• Solid understanding of image/video processing pipelines and IP integration.
• Excellent analytical, debugging, and communication skills.