As a Staff Engineer - ASIC SOC Verification, you will be responsible for designing and verifying complex ASIC SOC systems. You will work closely with cross-functional teams to develop and implement verification plans, scripts, and testbenches. The ideal candidate will have expertise in Verilog, SystemVerilog, and UVM, with a strong understanding of RTL design and verification methodologies.
Key Responsibilities:
- Design and develop verification plans, scripts, and testbenches for complex ASIC SOC systems.
- Collaborate with cross-functional teams to identify and prioritize verification requirements.
- Develop and maintain verification environments, including testbenches and constrained random testbenches.
- Identify and debug issues in the verification environment and provide solutions.
- Work with the design team to ensure that the design meets the verification requirements.
Requirements:
- 8+ years of experience in ASIC SOC verification.
- Expertise in Verilog, SystemVerilog, and UVM.
- Strong understanding of RTL design and verification methodologies.
- Experience with Python programming language.
- Excellent communication and collaboration skills.