As a Staff Engineer, ASIC Design Verification, you will be responsible for designing and verifying complex Application-Specific Integrated Circuits (ASICs) using Python, Verilog, and SystemVerilog. You will work closely with cross-functional teams to ensure high-quality designs that meet customer requirements. Your expertise in ASIC design verification will be crucial in identifying and resolving design issues, and ensuring that the final product meets the required specifications.
Key Responsibilities:
- Design and verify complex ASICs using Python, Verilog, and SystemVerilog.
- Collaborate with cross-functional teams, including design, verification, and manufacturing, to ensure high-quality designs.
- Identify and resolve design issues, and ensure that the final product meets the required specifications.
- Develop and maintain documentation, including design specifications, test plans, and verification reports.
- Stay up-to-date with industry trends and emerging technologies, and apply this knowledge to improve design and verification processes.
Requirements:
- Master's degree in Electrical Engineering, Computer Science, or related field.
- Minimum 8 years of experience in ASIC design verification, with a strong background in Python, Verilog, and SystemVerilog.
- Proven track record of delivering high-quality designs and resolving complex design issues.
- Excellent communication and collaboration skills, with the ability to work effectively with cross-functional teams.
- Strong problem-solving skills, with the ability to analyze complex design issues and develop effective solutions.