This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Staff ASIC Digital Engineer (STA and Sign-Off) based in India.
This is an outstanding opportunity for an experienced semiconductor professional to lead Static Timing Analysis (STA) and sign-off activities for advanced ASIC designs. In this role, you will play a critical part in ensuring timing integrity, performance optimization, and successful tape-outs for complex digital products built on cutting-edge process technologies. Working in a highly collaborative engineering environment, you will partner with design, verification, physical design, and DFT teams to solve challenging technical problems and drive innovation in timing methodologies. The position offers significant technical ownership, exposure to advanced nodes, and the opportunity to shape best practices that influence next-generation storage and memory technologies.
Accountabilities:
- Own and drive complete STA sign-off activities for ASIC designs, ensuring timing closure and design readiness for tape-out.
- Provide technical guidance to Physical Design and Place & Route teams on timing closure strategies and synthesis report analysis.
- Collaborate with IP, RTL, and design teams to develop, review, and optimize timing constraints and sign-off methodologies.
- Develop and implement advanced STA methodologies to meet the performance requirements of highly complex semiconductor designs.
- Perform detailed timing analysis, identify critical timing paths, and propose effective solutions to resolve timing violations.
- Create, enhance, and maintain STA scripts, automation frameworks, and tools to improve efficiency and scalability.
- Work closely with cross-functional teams, including verification, DFT, and physical implementation teams, to ensure seamless design integration.
- Prepare and present technical reports, timing sign-off documentation, and status updates to key stakeholders.
- Drive continuous improvement initiatives by incorporating industry best practices and emerging timing analysis techniques.
- Mentor engineering teams and foster a culture of collaboration, innovation, and technical excellence.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Electronics, or a related discipline.
- Minimum of 8 years of experience in Static Timing Analysis and ASIC timing sign-off activities.
- Proven experience leading end-to-end STA sign-off for complex semiconductor projects.
- Strong expertise with industry-standard STA tools such as Synopsys PrimeTime, Cadence Tempus, and Constraints Manager.
- Deep understanding of digital design principles, synthesis, physical design flows, and semiconductor manufacturing processes.