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Sr Principal ASIC FPGA Engineer - General Dynamics Mission Systems
Software Engineer
Lead complex ASIC and FPGA development, driving high‑performance, high‑reliability designs for defense systems using Verilog/VHDL, RTL, and advanced timing closure techniques.
About the role
Key Responsibilities
- Architect and implement end‑to‑end ASIC and FPGA solutions for mission‑critical defense applications.
- Lead RTL design, synthesis, place‑and‑route, and timing closure for high‑speed, low‑power circuits.
- Develop and maintain verification environments using UVM, SystemVerilog, and simulation tools.
- Collaborate with cross‑functional teams on requirements, architecture, and design reviews.
- Ensure compliance with DoD security and quality standards, including TS/SCI clearance processes.
Requirements
- Bachelor’s degree in Electrical or Computer Engineering (or related field) with 10+ years of ASIC/FPGA experience, or Master’s with 8+ years.
- Proficiency in Verilog/VHDL, RTL design, and advanced timing analysis.
- Strong background in simulation, verification, and design for manufacturability.
- Experience with high‑speed serial interfaces and low‑power design techniques.
- Ability to obtain and maintain a U.S. Department of Defense TS/SCI clearance.