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Sr. Engineer II - Verification - Microchip Technology
Software Engineer
Senior Verification Engineer driving robust test environments for ASIC and FPGA designs using SystemVerilog, UVM, and advanced simulation techniques to ensure product reliability and performance.
About the role
Key Responsibilities
- Design, develop, and maintain comprehensive verification environments for complex ASIC and FPGA IP blocks.
- Implement UVM-based testbenches, coverage models, and assertion libraries to validate functional and timing specifications.
- Collaborate with RTL, synthesis, and physical teams to troubleshoot and resolve design issues early in the development cycle.
- Generate and analyze simulation results, coverage reports, and debug logs to drive design improvements.
- Mentor junior verification engineers and contribute to best‑practice documentation and process enhancements.
Requirements
- 5+ years of experience in ASIC/FPGA verification using SystemVerilog and UVM.
- Strong background in HDL design, simulation, and debugging.
- Proficiency with industry tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
- Excellent problem‑solving skills and ability to work in a fast‑paced, cross‑functional environment.
- Effective communication skills and a collaborative mindset.
Skills
machine learningpythonlinuxvhdlverilog