Lead verification of advanced microcontroller IP using Verilog, SystemVerilog, and UVM to ensure robust ASIC and FPGA implementations for automotive and IoT applications.
About the role
Key Responsibilities
Develop and maintain comprehensive verification environments for IP blocks using SystemVerilog and UVM.
Design, implement, and execute testbenches to validate functional and timing specifications of ASIC and FPGA targets.
Collaborate with RTL designers to troubleshoot and resolve design issues, providing actionable feedback.
Integrate simulation results with formal verification and coverage analysis tools to achieve high-quality deliverables.
Document verification strategies, test plans, and defect reports for cross‑functional review.
Requirements
Strong experience in hardware design verification, with a focus on ASIC and FPGA IP.
Hands‑on experience with simulation tools such as Questa/SimVision or VCS.
Knowledge of coverage-driven verification and formal methods is a plus.
Excellent problem‑solving skills and ability to work collaboratively in a fast‑paced R&D environment.