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Silicon Micro-architecture and RTL Lead - Google
Software Engineer
Lead the micro‑architecture and RTL development of high‑performance ASICs, driving design, verification, synthesis and integration using Verilog/SystemVerilog, VHDL and Python scripting.
About the role
Key Responsibilities
- Define and implement micro‑architecture for complex ASIC IP blocks and subsystems.
- Lead RTL development in Verilog, SystemVerilog, and VHDL, ensuring coding standards and performance targets.
- Develop and execute comprehensive verification plans, including testbench creation, simulation, and coverage analysis.
- Perform synthesis, timing, and power analysis, collaborating with physical design to meet timing closure.
- Drive Design‑for‑Testing strategies and integrate DFT features into the flow.
- Coordinate SoC integration, bus architecture, and NoC connectivity, working closely with hardware and software teams.
Requirements
- 10+ years of ASIC development experience with Verilog/SystemVerilog and VHDL.
- Strong background in micro‑architecture, design IP creation, and subsystem integration.
- Proficiency in design verification, synthesis, timing/power analysis, and DFT methodologies.
- Experience scripting in Python or Perl to automate flows and analyses.
- Hands‑on experience with SoC design, bus protocols, NoC fabrics, and accelerator or memory blocks.