onsite
Senior Technical Architect - RTL Design - HCLTech
Solutions Architect
Lead high‑performance, low‑power RTL design projects, defining micro‑architecture, driving ASIC/SoC flows, and managing a team of senior engineers while ensuring timing closure and IP integration across multiple concurrent projects.
About the role
Key Responsibilities
- Define micro‑architecture specifications for high‑performance, low‑power digital blocks and subsystems.
- Lead full‑chip RTL integration, synthesis, and timing constraint development for ASIC/SoC projects.
- Perform static timing analysis, resolve placement & routing congestion, and ensure timing closure.
- Integrate and validate IP cores such as PCIe, DDR, and Ethernet within the design flow.
- Mentor and manage a team of 5–6 senior leads and entry‑level engineers across multiple simultaneous projects.
Requirements
- 8–14 years of experience in RTL design and ASIC/SoC development.
- Proficiency in synthesis tools, timing analysis, and scripting for RTL workflows.
- Strong knowledge of IP integration and low‑power design techniques.
- Demonstrated leadership in managing technical teams and delivering complex projects on schedule.