onsite
Senior Technical Architect - Design Validation - HCLTech
Solutions Architect
Senior Technical Architect with 8‑14 years of experience leading high‑performance, low‑power digital design validation, RTL integration, and ASIC/SoC flow automation using Verilog, synthesis scripting, and IP integration (PCIe, DDR, Ethernet).
About the role
Key Responsibilities
- Define micro‑architecture specifications for high‑performance, low‑power digital blocks and subsystems.
- Lead full‑chip RTL integration, ensuring seamless incorporation of IPs such as PCIe, DDR, and Ethernet.
- Drive ASIC/SoC development flow, including synthesis, timing constraint creation, static timing analysis closure, and congestion resolution.
- Develop and maintain synthesis and timing scripts (Python/Tcl) to automate build and verification processes.
- Mentor and manage a team of 5‑6 senior leads and junior engineers across multiple concurrent projects.
Requirements
- 8–14 years of hands‑on experience in RTL design, verification, and full‑chip integration.
- Strong background in ASIC/SoC flow, synthesis, STA, and resolving P&R congestion.
- Proficiency with Verilog/SystemVerilog and scripting languages (Python, Tcl) for automation.
- Demonstrated experience integrating high‑speed interfaces such as PCIe, DDR, and Ethernet.
- Proven leadership skills managing cross‑functional teams and delivering multiple projects simultaneously.
Skills
awsazuresystem design