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Senior Staff Engineer - R&D Engineering - Synopsys
Software Engineer
Lead advanced R&D to accelerate Verilog/SystemVerilog simulation using C++ compiler techniques and GPU‑based multi‑core hardware acceleration, driving performance and reliability gains for next‑generation design tools.
About the role
Key Responsibilities
- Architect and implement high‑performance C++ compiler extensions to optimize Verilog/SystemVerilog simulation pipelines.
- Design and prototype GPU‑based multi‑core hardware accelerators for simulation acceleration.
- Collaborate with cross‑functional teams to integrate new acceleration modules into the core simulation engine.
- Analyze performance bottlenecks, propose solutions, and benchmark improvements against industry standards.
- Mentor junior engineers and lead technical discussions on compiler and hardware acceleration strategies.
Requirements
- 10+ years of software engineering experience with deep expertise in C++ and compiler construction.
- Strong background in digital design languages (Verilog/SystemVerilog) and simulation tools.
- Hands‑on experience with GPU programming (CUDA/OpenCL) and multi‑core hardware acceleration.
- Proven track record of delivering performance‑critical solutions in a large‑scale engineering environment.
- Excellent problem‑solving skills and ability to communicate complex technical concepts clearly.