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Senior FPGA Engineer - ZENOVO
Software Engineer
Senior FPGA Engineer responsible for designing, implementing, and verifying high‑performance FPGA solutions using Verilog/VHDL and Vivado, driving architecture decisions and ensuring robust system integration across the product lifecycle.
About the role
Key Responsibilities
- Lead the design and implementation of FPGA architectures for cutting‑edge products, translating requirements into RTL specifications.
- Develop and maintain Verilog/VHDL code, perform synthesis, place‑and‑route, and timing analysis using Vivado.
- Collaborate with hardware and software teams to integrate FPGA modules into system‑level designs and validate functionality through simulation and hardware testing.
- Optimize designs for performance, power, and area, applying advanced techniques such as clock‑domain crossing, pipelining, and resource sharing.
- Document design decisions, create technical specifications, and provide mentorship to junior engineers.
Requirements
- 5+ years of FPGA design experience with a strong background in Verilog/VHDL and RTL design.
- Proficient in Vivado (or equivalent) for synthesis, implementation, and timing closure.
- Deep understanding of digital design principles, clock management, and signal integrity.
- Experience with system integration, hardware debugging, and testbench development.
- Excellent problem‑solving skills and ability to work independently in a fast‑paced environment.