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Senior FPGA Engineer VHDL/Verilog - Agad Technology
Software Engineer
Lead complex FPGA development using VHDL/Verilog, driving RTL design, timing closure, and integration with embedded systems. Drive high-performance, low-power solutions for advanced digital products.
About the role
Key Responsibilities
- Design, implement, and verify RTL modules in VHDL and Verilog for high‑performance FPGA solutions.
- Perform timing analysis, power optimization, and resource utilization to meet stringent performance targets.
- Collaborate with ASIC and system teams to ensure seamless integration and interface compliance.
- Develop and maintain testbenches, simulation models, and automated verification flows.
- Mentor junior engineers and review design documentation for quality and consistency.
Requirements
- 5+ years of FPGA design experience with VHDL/Verilog.
- Strong background in RTL design, timing closure, and power analysis.
- Experience with industry tools (Vivado, Quartus, ModelSim, Questa).
- Solid understanding of embedded systems and interface protocols (AXI, PCIe, DDR).
- Excellent problem‑solving skills and a proactive, collaborative attitude.