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Senior FPGA Engineer - Raytheon
Software Engineer
Lead complex FPGA development for defense systems, driving RTL design, high‑speed serial interfaces, and timing closure using VHDL/Verilog and advanced simulation tools.
About the role
Key Responsibilities
- Design, implement, and verify RTL for mission‑critical FPGA solutions using VHDL and Verilog.
- Develop and maintain high‑speed serial interfaces (PCIe, Ethernet, JESD204) ensuring timing closure and signal integrity.
- Collaborate with ASIC and system teams to integrate FPGA modules into larger defense platforms.
- Lead simulation and formal verification efforts, utilizing tools such as ModelSim, Questa, and UVM.
- Provide technical mentorship to junior engineers and conduct design reviews.
Requirements
- 5+ years of FPGA design experience in a defense or aerospace environment.
- Proficiency in VHDL/Verilog, RTL synthesis, and timing analysis.
- Strong knowledge of high‑speed serial protocols and signal‑integrity techniques.
- Experience with simulation, formal verification, and UVM methodology.
- U.S. citizenship and ability to obtain a DoD Secret clearance.