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Senior FPGA Architect - Teradyne
Software Engineer
Senior FPGA Architect leading complex FPGA architecture design, RTL development, and timing closure for high‑performance test and automation solutions, leveraging Verilog/VHDL and ASIC expertise.
About the role
Key Responsibilities
- Design, implement, and optimize FPGA architectures for next‑generation test and automation platforms.
- Develop RTL in Verilog and VHDL, ensuring functional correctness and meeting performance targets.
- Perform detailed timing analysis, power optimization, and resource utilization studies to achieve design closure.
- Collaborate with ASIC and embedded software teams to integrate FPGA solutions into larger system architectures.
- Lead design reviews, mentor junior engineers, and drive continuous improvement of FPGA development processes.
Requirements
- 10+ years of FPGA design experience with deep knowledge of Verilog/VHDL and RTL design.
- Proven track record in high‑speed serial interfaces, timing closure, and power optimization.
- Strong understanding of ASIC design flow and embedded system integration.
- Excellent problem‑solving skills and ability to work in a fast‑paced, cross‑functional environment.
- Effective communication skills for technical documentation and stakeholder engagement.