remote
Senior Engineer, Post Silicon Validation - Renesas
Software Engineer
Lead post‑silicon validation for advanced semiconductor IP, driving verification, debugging, and performance tuning using SystemVerilog, UVM, and Python across ASIC and FPGA platforms.
About the role
Key Responsibilities
- Design, implement, and execute comprehensive post‑silicon validation plans for complex SoC and MCU IP blocks.
- Develop and maintain high‑coverage SystemVerilog/UVM testbenches to validate silicon functionality and performance.
- Collaborate with design, firmware, and hardware teams to diagnose and resolve silicon bugs, leveraging FPGA prototyping and debug tools.
- Analyze silicon data, generate detailed defect reports, and recommend design or process improvements.
- Mentor junior engineers and contribute to best‑practice documentation for validation workflows.
Requirements
- 10+ years of experience in semiconductor post‑silicon validation, with deep expertise in SystemVerilog and UVM.
- Strong background in ASIC and FPGA design, including RTL verification and hardware debugging.
- Proficiency in Python for data analysis, automation, and scripting.
- Excellent problem‑solving skills and ability to work cross‑functionally in a fast‑paced environment.
- Effective communication skills, both written and verbal, to convey complex technical findings.