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Senior Engineer, IPDev Layout - Micron Technology
Software Engineer
Senior Engineer, IPDev Layout responsible for high‑performance silicon layout, timing closure, and physical design of memory IP blocks using advanced EDA tools and VLSI methodologies.
About the role
Key Responsibilities
- Design, review, and optimize physical layouts for memory IP blocks, ensuring compliance with design rules and performance targets.
- Perform timing analysis, power estimation, and signal integrity checks to achieve target clock speeds and power budgets.
- Collaborate with RTL, synthesis, and verification teams to resolve design issues and integrate new features.
- Generate and maintain detailed layout documentation, including GDSII, LVS, and DRC reports.
- Lead design rule checks (DRC) and layout versus schematic (LVS) verification, and drive continuous improvement of physical design flows.
Requirements
- BS/MS in Electrical Engineering, Computer Engineering, or related field.
- 5+ years of experience in VLSI physical design for memory or high‑performance IP.
- Proficiency with industry EDA tools (Cadence, Synopsys, Mentor) and layout editors.
- Strong knowledge of timing closure, power optimization, and signal integrity.
- Excellent communication skills and ability to work cross‑functionally in a fast‑paced environment.