Senior Design Verification Engineer

We are seeking a Senior Design Verification Engineer to join our team in Jalisco, Mexico. The successful candidate will be responsible for developing and executing verification plans for complex digital designs, working closely with cross-functional teams to ensure timely and successful product releases. The ideal candidate will have a strong background in digital design, verification methodologies, and programming languages such as Python and Verilog.

Key Responsibilities:

• Develop and execute verification plans for complex digital designs
• Collaborate with cross-functional teams to ensure timely and successful product releases
• Design and implement verification environments using UVM and SystemVerilog
• Develop and maintain testbenches and test programs using Python and Verilog
• Identify and report design bugs and defects, working with design teams to resolve issues

Requirements:

• Master's degree in Electrical Engineering, Computer Science, or related field
• Minimum 5 years of experience in digital design verification
• Strong background in digital design, verification methodologies, and programming languages such as Python and Verilog
• Experience with UVM and SystemVerilog
• Excellent communication and collaboration skills