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Senior Backend Engineer - ASIC / Physical Design - Fraunhofer-Gesellschaft e.V. Zentrale Munchen
Backend Engineer
Lead backend engineering for ASIC and physical design projects, driving RTL development, synthesis, place‑and‑route, and verification using Python, C++ and industry‑standard EDA tools.
About the role
Key Responsibilities
- Design, implement, and optimize RTL modules in Verilog/VHDL for ASIC projects.
- Lead synthesis, placement, routing, and timing closure using EDA tools such as Synopsys, Cadence, or Mentor.
- Develop Python and C++ scripts to automate design flows, generate reports, and integrate with verification frameworks.
- Collaborate with verification, floorplanning, and power teams to ensure design quality and manufacturability.
- Perform design reviews, debug hardware issues, and provide technical guidance to junior engineers.
Requirements
- 10+ years of experience in ASIC and physical design engineering.
- Strong proficiency in HDL (Verilog/VHDL), RTL design, and EDA toolchains.
- Solid programming skills in Python and C++ for automation and tooling.
- Experience with timing analysis, power optimization, and DFM/DFT practices.
- Excellent problem‑solving skills and ability to work in a fast‑paced research environment.