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Senior ASIC RTL Integration Engineer - Google
Implementation Engineer
Lead RTL integration for silicon projects, optimizing performance, power, and silicon success using Verilog/SystemVerilog, logic synthesis, and low‑power techniques while scripting in Python or Perl.
About the role
Key Responsibilities
- Design, verify, and integrate RTL modules for complex ASICs, ensuring silicon‑ready quality and performance targets.
- Apply advanced logic synthesis and optimization techniques to meet power, area, and timing constraints.
- Collaborate with IP, verification, and physical teams to resolve integration issues and drive silicon success.
- Develop and maintain Python/Perl scripts for automation of RTL flow, testbench generation, and data analysis.
- Document design decisions, create integration reports, and support post‑silicon debugging.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (Master’s/PhD preferred).
- 8+ years of experience in digital logic design, RTL design, and silicon integration.
- Proficiency in Verilog and SystemVerilog with a strong understanding of RTL design principles.
- Hands‑on experience with logic synthesis, performance optimization, and low‑power design techniques.
- Strong scripting skills in Python or Perl for automation and data processing.