Senior ASIC Design Verification Engineer

As a Senior ASIC Design Verification Engineer, you will be responsible for designing and verifying complex ASICs using industry-leading tools and methodologies. You will work closely with cross-functional teams to develop and implement verification strategies, debug and resolve complex issues, and ensure high-quality design delivery.

Key Responsibilities

• Design and develop verification environments using Python, Verilog, and SystemVerilog.
• Collaborate with design teams to develop and implement verification strategies.
• Debug and resolve complex issues using UVM and other verification tools.
• Develop and maintain verification plans, testbenches, and test cases.
• Ensure high-quality design delivery through thorough verification and validation.

Requirements

• 8+ years of experience in ASIC design verification.
• Strong knowledge of Verilog, SystemVerilog, and UVM.
• Experience with Python scripting and automation.
• Excellent problem-solving and debugging skills.
• Strong communication and collaboration skills.