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Senior ASIC Design Engineer - Cloud Scale Machine Learning Acceleration - Amazon
ML Engineer
Design and deliver high‑performance ASICs for cloud‑scale machine‑learning acceleration, leveraging SystemVerilog, RTL verification, and Cadence tools while scripting flows in Python.
About the role
Key Responsibilities
- Lead the architecture, RTL development, and physical implementation of ASICs that power large‑scale machine‑learning inference and training workloads.
- Collaborate with cross‑functional hardware, software, and algorithm teams to define performance, power, and area targets.
- Develop and maintain verification environments using SystemVerilog/UVM to ensure functional correctness and timing closure.
- Utilize Cadence (or Synopsys) design suites for synthesis, place‑and‑route, timing analysis, and sign‑off, driving design optimizations for cloud‑scale efficiency.
- Automate design‑flow tasks and data analysis with Python scripts, improving productivity and repeatability.
Requirements
- Bachelor’s or higher in Electrical Engineering, Computer Engineering, or related field with 5+ years of ASIC design experience.
- Proficiency in SystemVerilog RTL coding, synthesis, and timing closure for high‑performance compute blocks.
- Hands‑on experience with industry‑standard EDA tools (Cadence, Synopsys, Mentor) for full‑chip implementation.
- Strong scripting skills in Python for design automation and data processing.
- Demonstrated ability to work on machine‑learning accelerator architectures and optimize for power, performance, and area at cloud scale.