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Scientist- ASIC Verification, Interface IP- PCIe/CXL - Synopsys
Software Engineer
Experienced ASIC Verification Engineer specializing in PCIe and CXL Interface IP, building robust verification environments using SystemVerilog, UVM, and Python scripting to ensure high‑quality silicon delivery.
About the role
Key Responsibilities
- Design, develop, and maintain comprehensive verification environments for PCIe and CXL interface IP blocks.
- Implement testbenches and verification components using SystemVerilog and the Universal Verification Methodology (UVM).
- Create and execute directed and constrained-random test suites, analyzing coverage and debug results to close verification gaps.
- Collaborate with design, architecture, and software teams to define verification plans, specifications, and sign‑off criteria.
- Automate regression flows and result reporting with Python scripts and CI/CD tools.
Requirements
- 10+ years of hands‑on ASIC verification experience, preferably with high‑speed interface protocols.
- Deep knowledge of PCIe (Gen3/Gen4) and CXL specifications and associated verification challenges.
- Proficiency in SystemVerilog and UVM, including stimulus generation, scoreboard, and coverage models.
- Strong scripting skills in Python for automation, data analysis, and tool integration.
- Experience with industry‑standard verification tools and methodologies, and ability to work effectively in cross‑functional teams.