We are sharing a specialised part-time consulting opportunity for experienced digital chip design and verification professionals with strong backgrounds in RTL development, SystemVerilog, ASIC workflows, verification infrastructure, and frontier silicon engineering workflows.
This role supports current and upcoming remote consulting opportunities focused on structured silicon design review, RTL development, design verification, simulation debugging, technical documentation, and high-quality project execution. Selected professionals will apply their digital design or verification expertise to review realistic chip-design scenarios, evaluate technical outputs, prepare structured written deliverables, and support accurate, evidence-based silicon engineering workflows.
Key Responsibilities
Professionals in this role may contribute to:
RTL Design & Digital Architecture Review
- Review digital design scenarios involving RTL modules, FSMs, datapaths, pipelines, FIFOs, arbiters, clock and reset domains, bus protocols, and SoC-level design components
- Evaluate RTL implementations against design requirements, architectural intent, timing considerations, synthesis expectations, and technical constraints
- Support structured review of Verilog and SystemVerilog code, design documentation, simulation outputs, waveform traces, and debug materials
- Identify logic issues, integration gaps, unclear tradeoffs, and expected RTL design outcomes
ASIC Flow, Debug & Implementation Support
- Review ASIC design workflow materials involving lint, synthesis, timing analysis, CDC, DFT-aware design, waveform debug, and simulation logs
- Evaluate design outputs against source documentation, tool reports, design constraints, and implementation expectations
- Support structured review of materials connected to common EDA tools for simulation, waveform viewing, linting, CDC analysis, synthesis, and timing review
- Prepare clear written explanations for design decisions, debug findings, and technical tradeoffs based on source materials and verifiable criteria
Design Verification & Coverage Review
- Review verification scenarios involving SystemVerilog, UVM, reusable verification components, testbench infrastructure, constrained-random testing, SVA assertions, and functional coverage
- Evaluate verification plans, test cases, scoreboards, reference models, coverage reports, regression results, and debug reports against defined verification goals
- Support structured review of coverage closure workflows, regression flows, formal verification materials, and verification IP
- Maintain accuracy, consistency, and professional judgment across submitted work