Principal/Senior High-Speed Analog Layout Engineer - Celero Communications

Key Responsibilities

• Lead the full‑stack layout design of high‑speed analog and mixed‑signal IP blocks, ensuring performance, area, and manufacturability targets are met.
• Collaborate closely with schematic, verification, and physical teams to translate functional specifications into robust, manufacturable layouts.
• Perform detailed EM, DRC, LVS, and parasitic extraction analyses, iterating layouts to optimize signal integrity and power integrity.
• Mentor junior layout engineers, providing technical guidance and best‑practice training on layout techniques and tool workflows.
• Drive process development, including design rule checks, layout‑vs‑schematic automation, and documentation standards.

Requirements

• 10+ years of experience in high‑speed analog and mixed‑signal layout for semiconductor IP.
• Expertise in Cadence Virtuoso, Spectre, and EM tools such as ANSYS HFSS or Keysight ADS.
• Strong understanding of RF and power‑integrity considerations in high‑speed designs.
• Proven ability to lead cross‑functional teams and deliver complex projects on schedule.
• Excellent communication skills and a collaborative mindset.