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Principal FPGA Engineer - Teledyne FLIR
Software Engineer
Lead complex FPGA development for high-reliability aerospace and defense systems, driving RTL design, synthesis, and timing closure while collaborating with cross‑functional teams to deliver cutting‑edge hardware solutions.
About the role
Key Responsibilities
- Architect and implement RTL solutions in Verilog/VHDL for mission‑critical FPGA platforms.
- Lead synthesis, place‑and‑route, and timing closure activities to meet stringent performance and reliability targets.
- Collaborate with hardware, firmware, and software teams to integrate FPGA logic with embedded C/C++ drivers.
- Perform high‑speed serial interface design and verification (PCIe, Ethernet, JESD204).
- Provide technical mentorship and code reviews for junior engineers.
Requirements
- 10+ years of FPGA design experience in aerospace/defense or similar high‑reliability domains.
- Expertise in Verilog/VHDL, RTL design, synthesis tools (Vivado, Quartus), and timing analysis.
- Strong knowledge of high‑speed serial protocols and embedded C integration.
- Excellent problem‑solving skills and ability to work independently in a contractor role.