Principal Engineer - Memory Circuit Design Verification

As a Principal Engineer - Memory Circuit Design Verification, you will be responsible for designing and verifying complex memory circuits using Python and Verilog/SystemVerilog. You will work closely with cross-functional teams to develop and implement verification plans, scripts, and testbenches to ensure the quality and reliability of our memory products. You will also be responsible for identifying and resolving complex technical issues, and collaborating with design teams to resolve design and verification issues.

Key Responsibilities:

• Design and develop complex memory circuits using Python and Verilog/SystemVerilog.
• Develop and implement verification plans, scripts, and testbenches to ensure the quality and reliability of our memory products.
• Collaborate with cross-functional teams to identify and resolve complex technical issues.
• Work closely with design teams to resolve design and verification issues.
• Develop and maintain technical documentation and reports to track progress and issues.

Requirements:

• 8+ years of experience in memory circuit design and verification.
• Strong understanding of Verilog/SystemVerilog and Python programming languages.
• Experience with UVM (Universal Verification Methodology) and RTL (Register-Transfer Level) Design.
• Excellent problem-solving and analytical skills.
• Strong communication and collaboration skills.