Principal Engineer - ASIC Physical Design

We are seeking a Principal Engineer - ASIC Physical Design to join our team in Hyderabad. The successful candidate will be responsible for designing and developing complex ASICs using Python and HDL languages, with expertise in Cadence EDA tools and ASIC physical design. The ideal candidate will have a strong background in ASIC physical design, with experience in developing and implementing complex digital and analog circuits.

Key Responsibilities

• Design and develop complex ASICs using Python and HDL languages.
• Develop and implement complex digital and analog circuits using Cadence EDA tools.
• Collaborate with cross-functional teams to develop and implement ASIC physical design methodologies.
• Develop and maintain documentation for ASIC physical design processes and tools.
• Stay up-to-date with industry trends and advancements in ASIC physical design.

Requirements

• Master's degree in Electrical Engineering or Computer Science.
• Minimum 8 years of experience in ASIC physical design.
• Strong background in Python and HDL languages.
• Expertise in Cadence EDA tools and ASIC physical design methodologies.
• Excellent communication and collaboration skills.