Principal ASIC Engineer Reliability & Hardware Validation - Cisco
Hardware Engineer
We're looking for a Hardware Engineer focused on designing and building scalable technical solutions. This lead role requires 9+ years of relevant experience.
About the role
Qualification Strategy: Define and execute comprehensive product/process qualification plans for next-generation, high-power solutions (wafer/package level).
Reliability Execution: Drive robust, error-free HTOL, Burn-In, and stress testing (HAST, TC, HTS, ESD, LU, SER). Manage reliability suppliers and subcontractors to ensure adherence to qualification schedules.
Hardware Design& Validation: Lead hardware design, schematic generation, and design validation for service provider routing products. Manage board bring-up and debug processes.
Failure Analysis: Drive failure analysis activities and generate detailed qualification reports to ensure product integrity.
Multi-functional Collaboration: Partner with eCAD, FPGA, Power, Mechanical, Signal Integrity, and Manufacturing teams to support design-for-reliability and high-speed interface compliance.
Customer Support: Provide technical documentation and support for customer quality and reliability requirements.
Education: Master’s degree in electrical engineering, Computer Engineering, or a related field.
Experience: 10+ years of professional experience in semiconductor reliability and/or high-speed hardware design.
Reliability Expertise: Proven experience in developing high-power HTOL/Burn-In testing for advanced node products. Deep knowledge of JEDEC, AEC, and Telcordia standards.
Hardware Expertise: Hands-on experience with high-speed network interfaces, board design, and familiarity with tools such as Cadence Allegro.
Technical Skills: Experience with high-speed measurement equipment and automated test development. Ability to interpret sophisticated schematics and layouts. Proficiency in data analysis/debug and HTOL set-up
Education: PhD in Electrical or Computer Engineering.
Advanced Node Experience: Experience with 2nm/3nm Hyperscaler Multi-Chip-Modules and advanced packaging (CoWoS, SoIC, EMIB).
High-Speed Design: Deep expertise in >100Gbps system design, signal integrity, and power distribution. Knowledge of SerDes architecture (NRZ/PAM4 at 56G/112G/224G+), PCIe Gen5/6, and 800G Ethernet.
Programming: Proficiency in Python, Perl, TCL, or Verilog for scripting and automation.
Analytical Tools: Experience with JMP, Reliasoft, or Minitab for reliability statistical analysis.
Methodology: Understanding of FMEA processes, risk assessment, and reliability lifetime modeling.
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees