remote
Physical Design Technical Lead, ASIC, TPU - Google
Engineering Manager
Lead end‑to‑end physical design of high‑speed ASICs for TPU projects, driving floorplanning, placement, routing, and timing closure in advanced nodes while mentoring a team and automating workflows with Python.
About the role
Key Responsibilities
- Lead full‑chip and sub‑chip implementation from RTL to GDSII for high‑performance TPU ASICs.
- Drive floorplanning, placement, routing, and timing closure in advanced process nodes.
- Develop and maintain Python/Tcl/Perl scripts to automate design flows and improve yield.
- Collaborate with synthesis, verification, and packaging teams to ensure design integrity.
- Mentor and coach junior engineers, fostering best practices and continuous improvement.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (Master’s/PhD preferred).
- 10+ years of experience in physical design for high‑speed ASICs, including RTL2GDSII flow.
- Proficiency with Cadence Innovus, Synopsys tools, and advanced node design.
- Strong scripting skills in Python, Tcl, or Perl.
- Excellent communication, leadership, and problem‑solving abilities.