Lead Embedded CPU PPA Architect - AMD

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

THE ROLE:

We are seeking a lead PPA Architect to ensure that CPU Core & Cache complexes used in embedded products meets the product performance requirements while operating within reliability and system platform constraints. This is a technical leadership role ensuring interlock between CPU IP definition from the Cores design team and the Embedded BU’s unique per-product usage model and operating conditions, and the package & platform impact to the power delivery network and thermal management.

THE PERSON:

You will be a proven technical leader with the ability to drive cross-functional alignment and execution across architecture, physical design implementation, FW/BIOS, SIPI, and platform teams, ensuring timely closure and multi-dimensional alignment of reliability, power delivery, thermal management and performance constraints. You will also be highly organized and execution-driven, with demonstrated success owning end-to-end technical workstreams and driving closure of open issues, risks, and dependencies across program milestones.

KEY RESPONSIBILITIES:

Align Product Requirements with Cores IP

• Drive alignment on usage model (Product Lifetime, % residency in different CPU operating states, etc.), and operating condition constraints (Min/max ambient/case temp, TDC/EDC, customer-specific failure rate specs, etc.) as it impact achievable performance at power.
• Drive alignment on power delivery architecture, packaging infrastructure, and platform definition as it impacts assumed power delivery margins and define new margin requirements.
• Drive alignment on thermal modeling, packaging & platform definition as it impact assumed thermal operating margins and define new margin requirements.
• Translate product usage model, workload, and reliability requirements into IP performance, power, and thermal constraints.
• Drive alignment between Embedded BU product roadmap and available CPU IPs, providing critical technical feedback to Embedded product teams and CPU design teams.
• Drive alignment and lead technical reviews across the product definition stack: SoC architecture, physical design implementation, package design and platform definition.