remote
Lead Digital Verification Engineer - Cadence Design Systems
Software Engineer
Lead a high‑performance digital verification team, driving end‑to‑end verification of physical IP for industry‑standard protocols using SystemVerilog, UVM, and Python to deliver robust, scalable solutions on schedule.
About the role
Key Responsibilities
- Lead the design, implementation, and maintenance of comprehensive UVM‑based testbenches for high‑performance physical IP.
- Collaborate with RTL, synthesis, and physical teams to define verification strategies and ensure coverage goals are met.
- Mentor and coach junior verification engineers, fostering best practices in testbench architecture and debugging.
- Analyze simulation results, identify root causes, and drive corrective actions to meet project milestones.
- Integrate Python scripting for test automation, data extraction, and reporting.
Requirements
- 5+ years of experience in digital verification of ASIC/FPGA IP using SystemVerilog and UVM.
- Strong background in physical design verification and industry‑standard protocols.
- Proficiency in Python for automation and data analysis.
- Excellent problem‑solving skills and ability to work independently in a fast‑paced environment.
- Effective communication skills and a track record of mentoring junior engineers.