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Lead Architect - Programmable Clock Architecture - AMD
Software Engineer
Lead Architect for Programmable Clock Architecture driving next‑generation AI, data center, PC, gaming, and embedded systems with expertise in FPGA, ASIC, and high‑speed clock distribution design.
About the role
Key Responsibilities
- Design and architect scalable programmable clock solutions for AI, data center, PC, gaming, and embedded platforms.
- Lead cross‑functional teams in RTL, Verilog, and SystemVerilog development, ensuring performance, power, and reliability targets.
- Collaborate with ASIC and FPGA teams to integrate clock distribution into silicon and programmable logic.
- Define and enforce design standards, methodologies, and best practices for high‑speed clocking.
- Mentor junior engineers and drive continuous improvement in design flow and toolchains.
Requirements
- 10+ years of experience in system architecture and embedded clock design.
- Proficiency in RTL, Verilog, SystemVerilog, and high‑speed design tools.
- Strong background in FPGA and ASIC development for AI and data center workloads.
- Excellent problem‑solving, communication, and leadership skills.