HBM SoC Physical Design Engineer

We are seeking an experienced HBM SoC Physical Design Engineer to join our team. The successful candidate will be responsible for designing and developing High-Bandwidth Memory (HBM) System-on-Chip (SoC) physical designs using Python, Verilog, and SystemVerilog. The ideal candidate will have a strong background in physical design, verification, and validation of complex SoCs.

The HBM SoC Physical Design Engineer will work closely with cross-functional teams to design and develop high-performance, low-power SoCs that meet the needs of our customers. The successful candidate will be responsible for:

• Designing and developing HBM SoC physical designs using Python, Verilog, and SystemVerilog.
• Verifying and validating SoC designs using Cadence and Synopsys tools.
• Collaborating with cross-functional teams to ensure design meets performance, power, and area (PPA) requirements.
• Developing and maintaining design documentation and technical notes.
• Participating in design reviews and providing technical guidance to junior engineers.

The successful candidate will have a strong background in physical design, verification, and validation of complex SoCs, as well as excellent communication and collaboration skills.

Requirements:

• Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in physical design, verification, and validation of complex SoCs.
• Strong background in Python, Verilog, and SystemVerilog.
• Experience with Cadence and Synopsys tools.
• Excellent communication and collaboration skills.