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FPGA Verification Engineer II - BAE Systems USA
Software Engineer
Mid‑level FPGA Verification Engineer responsible for developing and executing verification plans for high‑precision, high‑reliability electronic systems using SystemVerilog, UVM and scripting automation.
About the role
Key Responsibilities
- Develop and maintain comprehensive verification environments for FPGA designs using SystemVerilog and UVM.
- Create test plans, testbenches, and verification IP to validate functional and timing requirements.
- Run simulations, analyze waveforms, and debug issues with tools such as ModelSim and Questa.
- Collaborate with hardware, firmware, and software teams throughout the product lifecycle to ensure design intent and performance targets are met.
- Automate regression testing and result reporting using Python scripts and continuous‑integration frameworks.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
- 2+ years of hands‑on FPGA verification experience with SystemVerilog and UVM.
- Proficiency in simulation tools (ModelSim, Questa) and scripting languages (Python).
- Strong understanding of digital design concepts, timing analysis, and hardware debugging techniques.
- Excellent communication and teamwork skills for cross‑disciplinary collaboration.