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FPGA Engineering Manager
Engineering Manager
Lead a high‑performance FPGA engineering team to design, validate, and deploy cutting‑edge FPGA solutions for global space communication systems, driving innovation in RTL design, high‑speed serial interfaces, and rapid product delivery.
About the role
Key Responsibilities
- Lead and mentor a multidisciplinary FPGA team, setting technical direction and ensuring high‑quality deliverables.
- Architect and implement RTL designs in Verilog/SystemVerilog for phased‑array ground station subsystems.
- Drive the full FPGA development lifecycle: synthesis, place‑and‑route, timing closure, and board‑level integration.
- Collaborate with ASIC, RF, and software teams to define interface specifications and performance targets.
- Establish best practices for design review, verification, and documentation, and maintain a robust IP library.
- Champion continuous improvement initiatives, adopting new tools and methodologies to accelerate time‑to‑market.
Requirements
- 10+ years of FPGA design experience, with 5+ years in a leadership role.
- Deep expertise in Verilog/SystemVerilog, RTL design, and high‑speed serial protocols (e.g., JESD204, PCIe).
- Proficiency with industry toolchains (Xilinx Vivado, Intel Quartus, Synopsys Design Compiler).
- Strong communication skills and a proven track record of delivering complex projects on schedule.
- Experience in the aerospace or space communications domain is highly desirable.