FPGA AI/ML Engineer Part Time - Riverside Research
ML Engineer
Part‑time FPGA engineer focused on AI/ML acceleration, designing and optimizing hardware using Vivado, Vitis, VHDL and Verilog to solve complex scientific problems.
About the role
Key Responsibilities
Design, implement, and verify FPGA-based AI/ML accelerators using VHDL and Verilog.
Utilize Xilinx Vivado and Vitis toolchains to synthesize, place, and route high‑performance hardware.
Collaborate with software and systems teams to integrate FPGA modules into end‑to‑end solutions.
Optimize resource utilization and power consumption while meeting performance targets.
Document design decisions, test plans, and performance metrics for internal review.
Requirements
Proven experience with FPGA development, Vivado, Vitis, VHDL, and Verilog.
Strong understanding of AI/ML workloads and hardware acceleration concepts.
Ability to write clean, maintainable HDL code and perform thorough verification.
Excellent problem‑solving skills and attention to detail.
U.S. citizenship required; ability to work remotely or on site as needed.