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ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead - Cisco
Engineering Manager
Lead ASIC packaging and signal/power integrity engineering for high‑performance networking hardware, driving design, verification, and manufacturing excellence across silicon, optics, and PCB layers.
About the role
Key Responsibilities
- Lead cross‑functional teams in designing and validating ASIC packaging solutions that meet stringent signal and power integrity requirements for high‑speed networking products.
- Develop and maintain advanced simulation models (e.g., S‑parameter, EM, thermal) to predict and mitigate signal degradation, crosstalk, and power noise.
- Collaborate with silicon, RF, and PCB teams to integrate packaging constraints into system‑level designs, ensuring manufacturability and yield.
- Drive continuous improvement of design flows, tools, and best practices, including automated test benches and verification scripts.
- Mentor junior engineers, conduct design reviews, and provide technical guidance on packaging standards and industry trends.
Requirements
- 10+ years of hardware engineering experience with a focus on ASIC packaging, signal integrity, and power integrity.
- Proficiency in simulation tools such as Ansys HFSS, CST, or equivalent, and strong analytical skills for EM/thermal analysis.
- Deep understanding of PCB layout, high‑speed interconnects, and manufacturing processes for advanced packaging.
- Excellent communication skills and proven ability to lead multidisciplinary teams.
- Experience with AI/ML hardware platforms is a plus.
Skills
electrical engineering