Looking for an experienced senior verification engineer with > 10 years of experience in ASIC/SOC/IP/block level design and functional verification using system verilog/UVM.
- Good knowledge ASIC flow
- Hands on experience in RTL coding, Synthesis, CDC and LEC
- The ideal candidate will have strong command of UVM, advanced UVM and system Verilog
Key responsibilities:
- Work with the customer team on the RTL coding, CDC, Synthesis and DFT tasks.
- Understand the verification environment and test patterns and customer products and co-ordinate with the offshore team
- Need to more proactive in driving both onsite and offshore team ~10 to 20 members
- Guide the offshore team and guide them technically and help to co-ordinate with customer team.
- Possess deep knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB
- Strong debugging skills to address TB issues quickly and test failures.
- Take responsibility for verification closure by addressing coverage and managing bug reports
- proficiency in using industry standard EDA tools such as Questa, VCS or ModelSim
- Experience with scripting languages like python, perl or TCL for automation tasks
- Experience working with Japan customer is a must
Language Requirement:
- Bilingual English and Japanese (N3 and above)
Originally posted on Himalayas